Lower dielectric constant materials are desirable in semiconductor chip manufacture to reduce signal propagation delays and crosstalk in back-end-of-the-line (BEOL) and packaging interconnects. A reduction in dielectric constant invariably results in a corresponding reduction in a dielectric fracture resistance. This is particularly true with brittle oxide-like dielectrics where fracture resistance is directly related to bond density and strength. In particular, delaminations can occur around the chip with metal structures requiring redesign of the kerf region of the chip, which restricts the area available for kerf test structures.
One consequence of this reduction in fracture resistance is that with recent dielectrics the fracture resistance of BEOL structures has become lower than that of the silicon substrate on which they are fabricated. Thus, imperfections introduced into the chip structure by processes such as chip dicing and wire bonding preferentially propagate through BEOL interconnect structures causing chip failure.
Generally, the semiconductor chip is further attached and connected to a packaging structure by different processes such as C4 chip attachment or wire bonding. Because of different thermal expansion properties during thermal cycling of different materials in the packaged chip, the complex arrangement of materials in the packaging structure can produce significant stresses in the chip during a packaging process and/or under a use condition. These forces or stresses, are typically concentrated, and can cause an existing structure imperfection to become unstable and propagate.
Certain stress relief materials may be used in such packages. However, under most circumstances, materials are chosen to optimize other functions, such as electrical performance, or C4 fatigue life of the package and thus cannot be designed solely to reduce the stresses on the chip. Further, significant shear or tensile stresses are usually applied to the edge of a packaged chip. Thus, there is a need for providing a structure, which avoids chip packing interaction (CPI) failures due to propagation of pre existing cracks or other imperfections into active areas of the chip.
One approach is to increase the intrinsic toughness of the dielectric itself. As discussed above, this cannot be done throughout the chip without increasing the effective dielectric constant and hence compromising electrical performance. To increase the resistance to propagation of CPI cracks without affecting the chip's electrical performance, strengthening of the dielectric must be achieved locally at the perimeter of the chip. This could be achieved by applying separate masking and processing steps to the edge of the chip. However, such an approach is expensive and thus undesirable.
Another approach to inhibit the propagation of structure imperfections is to reduce the stresses at the tip of the structure imperfection so that a critical fracture stress can not be reached. This can be done by special design of the package with limited options.
In view of the above, there exists a need for a structure having enhanced resistance to crack propagation in the back-end-of-line dielectric materials and methods of manufacturing the same.